The invention relates to Programmable Logic Devices (PLDs). More particularly, the invention relates to a power on reset circuit for a PLD that provides hysteresis in a noisy power environment.
Programmable logic devices (PLDs) are a well-known type of digital integrated circuit that can be programmed to perform specified logic functions. One type of PLD, the field programmable gate array (FPGA), typically includes an array of configurable logic blocks (CLBs) surrounded by a ring of programmable input/output blocks (IOBs). The CLBs and IOBs are interconnected by a programmable interconnect structure. Some FPGAs also include additional logic blocks with special purposes (e.g. DLLs, RAM, and so forth).
The CLBs, IOBs, interconnect, and other logic blocks are typically programmed by loading a stream of configuration data into internal configuration memory cells that define how the CLBs, IOBs, and interconnect are configured. The configuration data can be read from memory (e.g., an external PROM) or written into the FPGA by an external device. The collective states of the individual memory cells then determine the function of the FPGA.
Another type of PLD is the Complex Programmable Logic Device, or CPLD. A CPLD includes two or more xe2x80x9cfunction blocksxe2x80x9d connected together and to input/output (I/O) resources by an interconnect switch matrix. Each function block of the CPLD includes a two-level AND/OR structure similar to those used in Programmable Logic Arrays (PLAs) and Programmable Array Logic (PAL) devices. In some CPLDs, configuration data is stored on-chip in non-volatile memory, then downloaded to volatile memory as part of an initial configuration sequence.
In each of these PLDs, the functionality of the device is controlled by data bits provided to the device for that purpose. The data bits can be stored in volatile memory (e.g., static RAM cells, as in FPGAs and some CPLDs), in non-volatile memory (e.g., FLASH memory or E-squared memory, as in some CPLDs), or in any other type of memory cell.
Every PLD, whatever its type, must at some point be xe2x80x9cpowered upxe2x80x9d, i.e., awakened from a zero power state to a point at which the power high voltage VDD reaches an acceptable operating voltage level. The power up reset sequence resets the PLD so the device will function properly. For example, during the power up reset sequence, the input/output (I/O) pins of the PLD are preferably tristated (i.e., no signal is applied to the output pins by the PLD logic), the internal memory cells are initialized, and a configuration state machine is initialized and made ready to configure the part with the configuration data provided to the device.
Once the power high voltage VDD is high enough for the transistors of the device to operate properly, the configuration state machine takes control of the configuration process and begins loading configuration data into the volatile memory cells. When all of the data has been loaded, the I/O pins are enabled, and the device is ready to begin performing its programmed functions.
Another reset process takes place when a device is powered down, i.e., the power high voltage VDD is brought from the operating voltage level back down to the zero power state (or below a triggering voltage level). During the power down reset sequence, the PLD detects that the power high voltage VDD has reached or is nearing an unacceptably low level and performs a sequence of operations such as saving current state information, informing other integrated circuits (ICs) to stop sending data to the PLD, and so forth.
The power up and power down reset procedures are complicated by the fact that power supplies can be xe2x80x9cnoisyxe2x80x9d, i.e., glitching significantly above and/or below the nominal voltage level. For example, during the power up sequence, VDD can rise above the acceptable level and then fall below this level one or more times before reaching the final operating voltage. Additionally, once at the operating voltage, VDD can glitch to below a power down triggering voltage. Similarly, during the power down sequence, VDD can fall below the acceptable level and then rise back above this level one or more times before reaching the zero power level. Therefore, it is desirable to provide hysteresis (i.e., protection against transmitting such glitches) to circuitry that controls the power-related reset functions in a PLD.
FIG. 1 shows exemplary power up and power down voltage levels for VDD and corresponding voltage levels on a power on reset signal called POR. When signal POR is high, the device undergoes a reset process as described above. Note that in this example the POR signal is active-high, although power on reset signals can be either active-high or active-low. When used as a signal name herein, the name xe2x80x9cPORxe2x80x9d indicates an active-high signal, while the name xe2x80x9cPORBxe2x80x9d is used for an active-low signal. However, when used as an adjective, the acronym POR is simply used as an abbreviated form of the phrase xe2x80x9cpower on resetxe2x80x9d.
As shown in FIG. 1, when VDD begins to ramp up from the zero volt power level, VDD first reaches a level called VCMOSmin (time T0). VCMOSmin is the minimum power high level at which CMOS logic will function. At the VCMOSmin power level, the POR signal changes to a high value and the PLD enters reset mode. Because the power to the POR signal generator is provided by VDD, the voltage level of POR tracks VDD and does not exceed VDD at any given time.
The voltage level of VDD (and the POR signal) rises past the voltage level VOPmin, which is the minimum voltage at which all of the PLD circuitry will operate. Because not all of the logic in the PLD is digital CMOS logic, VOPmin is higher than VCMOSmin. VDD and POR then continue to rise to the voltage level called VPOR (time T1). At voltage level VPOR, the PLD is considered to be successfully reset and the POR signal is removed (i.e., the active-high signal POR goes low again). The PLD loads the configuration data from non-volatile memory, then enters user mode, i.e., begins to performs its programmed functions. The applied voltage VDD continues to rise until it passes the specified minimum operating voltage, SpecVDDmin.
FIG. 1 also shows the consequences of glitches on the VDD power level. If VDD glitches down while the PLD is in operating mode, but does not fall below the VPOR voltage level (e.g., at times T2 and T3), the power on reset circuitry is not affected and the PLD continues to operate in user mode. If VDD glitches below the VPOR voltage level, as at time T4, the POR signal is forced high and the PLD goes through the reset sequence again.
The POR signal must remain high long enough for the power on reset sequence to be successfully concluded. In the example of FIG. 1, duration D1 between times T0 and T1 is long enough to complete the reset sequence. Similarly, duration D2 after time. T4 is long enough to complete the reset sequence. However, after time T5 there are several glitches that restart the reset sequence repeatedly until (after time T6) there is finally a duration D3 that is sufficient to successfully reset the PLD.
At time T7, the VDD power high voltage level falls below the VPOR power level, and signal POR is driven high. The power down reset sequence is initiated. Signal POR then follows power high VDD down to below the VCMOSmin power level (time T8), at which point signal POR goes low again. Note that in the example of FIG. 1 the triggering voltages for both rising and falling power levels are the same (VPOR). These power levels can be the same or different from each other.
A noisy power environment is a greater problem for PLD designers and users than was previously the case, because PLD operating voltages are lower than they used to be. Thus, the difference between the operating voltage and the threshold voltage of an N-channel transistor, for example, is decreasing. A xe2x80x9cglitchxe2x80x9d that can inadvertently change the state of a memory cell, for example, can more easily occur with a lower operating voltage. Threshold voltages are also decreasing, which means that a minor change to the input voltage level of a transistor can undesirably change the state of the transistor.
Power high VDD can ramp up quickly or slowly, in a period of time ranging from a few microseconds to as much as several seconds. While PLD manufacturers generally specify a minimum VDD ramp rate, a slower ramp rate is desirable in some applications. In other applications, VDD ramps up in a staircase fashion, with intervals of rising power levels alternating with intervals where the power level remains flat. When VDD ramps up very slowly or in staircase fashion, existing PLDs may not reset properly. Further, current consumption can be very high during these slow reset processes. As a result of this high current consumption, the VDD ramp up is further slowed, and can even stop altogether, such that the device never enters the user mode.
Clearly, it is desirable to provide power on reset circuitry that generates a clean (glitch-free) POR signal in a noisy power environment. It is also desirable to provide power on reset circuitry that performs this function over a wide range of temperatures, process corners, and rising and falling VDD ramp rates.
The invention provides a power on reset (POR) generator circuit that is very stable over a wide range of power up and power down situations. The circuit of the invention includes a modified bandgap POR circuit in series with a modified RC POR circuit.
During a fast or a slow power up, the circuit of the invention behaves like a traditional bandgap POR circuit, providing a POR signal when the voltage on an internal node rises higher than a reference voltage level. However, the circuit of the invention also provides a capacitor on the bandgap output signal (from the modified RC POR circuit coupled in series with the bandgap output signal). During a fast power up, the capacitor ensures that the POR signal remains active long enough to reset the associated circuitry. During a slow power up, the capacitor prevents glitches in the bandgap output signal from being passed to the POR output signal. A feedback pulldown optionally included in the bandgap portion of the circuit also helps to prevent glitches from reaching the POR output signal by increasing the voltage level on the internal node after the reference voltage is exceeded.
When the power up ramp rate is in the intermediate range, conventional POR circuits sometimes do not issue a POR pulse at all, depending on the size of the capacitor. Because of the series configuration of the two sub-circuits, the present invention is not subject to this limitation.
According to one embodiment of the invention, a power on reset (POR) generator circuit includes a reference voltage input terminal, a bandgap POR circuit having an input terminal coupled to the reference voltage input terminal, and an RC POR circuit having an input terminal coupled to an output terminal of the bandgap POR circuit. An output terminal of the RC POR circuit is coupled to a POR output terminal of the POR generator circuit. One embodiment of the invention also includes a reference voltage generator circuit driving the reference voltage input terminal of the POR generator circuits.
According to one embodiment, the bandgap POR circuit includes a comparator circuit and two resistive elements coupled in series between power high VDD and ground. The comparator circuit has a first input terminal coupled to the reference voltage input terminal, a second input terminal coupled to a first node between the two resistive elements, and an output terminal coupled to the output terminal of the bandgap POR circuit.
Some embodiments also include a third resistive element coupled between the second resistive element and ground. A pulldown circuit is coupled to a second node between the second and third resistive elements, and a control terminal of the pulldown circuit is coupled to the output terminal of the comparator circuit.
According to one embodiment, the RC POR circuit includes a third node, a resistor coupled between the output terminal of the bandgap POR circuit and the third node, a capacitor coupled between the third node and ground, and a buffer driven by the third node and providing a POR output signal to the output terminal of the RC POR circuit.
Another embodiment of the invention provides a programmable logic device (PLD) that includes a configuration memory array, a configuration state machine, a power high VDD input terminal, and a power on reset (POR) generator circuit. The POR generator circuit provides a POR output signal to POR input terminals of the configuration memory array and the configuration state machine. The POR generator circuit is substantially as described above.
In some embodiments, the configuration memory array includes a volatile memory array and a non-volatile memory array, each having a POR input terminal coupled to the POR output terminal of the POR generator circuit. Various other embodiments include other circuits having input terminals coupled to the POR output terminal of the POR generator circuit. These circuits can include, for example, flip-flops and latches, input/output logic blocks, default logic functions and paths, and/or an off-chip communications circuit.
Some embodiments of the invention provide a system that includes an integrated circuit (IC) having a POR input terminal, and a PLD that drives the POR input terminal. The PLD includes a configuration memory array, a configuration state machine, a power high VDD input terminal, and a POR generator circuit. The POR generator circuit provides a POR output signal to POR input terminals of the configuration memory array, the configuration state machine, and the IC. The POR generator circuit can be, for example, substantially as described above.
According to one embodiment, the PLD includes an off-chip communication circuit having an input terminal coupled to the POR output terminal of the POR generator circuit and also having a xe2x80x9creadyxe2x80x9d output terminal. The ready output terminal is coupled to a ready input terminal of the IC. In some embodiments, the PLD includes other elements coupled to receive the POR signal, such as those described above.